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64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No. 0.01 Initial Draft 1. Editorial chage 0.80Typ --> 0.45 +/-0.05 (page12, Ball Dimension) Before dimension : History Draft Date Dec. 2004 Remark Preliminary
0.80 Typ.
0.65 Typ.
0.2
After dimension :
June. 2005
Preliminary
0.450 +/- 0.05
0.65 Typ.
2. Added Speed Product(100MHz CL2) (see to Page 02)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / June. 2005 1
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
DESCRIPTION
The Hynix HY5V66E(L)F6(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V66E(L)F6(P) is organized as 4banks of 1,048,576 x 16. HY5V66E(L)F6(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
* * * * * * Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 60 Ball FBGA (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM * Internal four banks operation * Burst Read Single Write operation Programmable CAS Latency; 2, 3 Clocks * * * Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No. HY5V66E(L)F6(P)-5 HY5V66E(L)F6(P)-6 HY5V66E(L)F6(P)-7 HY5V66E(L)F6(P)-H HY5V66E(L)F6(P)-P
Note: 1. HY5V66EF6 Series: Normal power, Leaded. 2. HY5V66ELF6 Series: Low power, Leaded. 3. HY5V66EF6P Series: Normal power, Lead Free. 4. HY5V66ELF6P Series: Low power, Lead Free.
Clock Frequency 200MHz 166MHz 143MHz 133MHz 100MHz
CL
Organization
Interface
Package
3
4Banks x 1Mbits x16
LVTTL
60 Ball FBGA
2
Rev. 0.2 / June. 2005
2
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
BALL CONFIGURATION
VDD
A1
A10
BA0
/CS
/CAS
/WE
NC
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
VDD
7 6 5
A3
A2
A0
BA1
NC
/RAS
LDQM
VDD
NC
VSSQ
VDDQ
DQ4
VSSQ
VDDQ
DQ0
Bottom View
4 3
A4
A5
A7
A9
NC
CLK
UDQM
VSS
NC
VDDQ
VSSQ
DQ11
VDDQ
VSSQ
DQ15
2 1
VSS
A6
A8
A11
CKE
NC
NC
NC
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
VSS
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
BALL DESCRIPTION
SYMBOL CLK CKE CS BA0, BA1 A0 ~ A11 RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC
Rev. 0.2 / June. 2005
TYPE INPUT INPUT INPUT INPUT INPUT INPUT INPUT I/O SUPPLY SUPPLY -
DESCRIPTION Clock: The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among (deep) power down, suspend or self refresh Chip Select: Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7 Auto-precharge flag: A10 Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details Data Mask: Controls output buffers in read mode and masks input data in write mode Data Input / Output: Multiplexed data input / output pin Power supply for internal circuits Power supply for output buffers No connection : These pads should be left unconnected
3
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row Counter
CLK CKE
State Machine Row Active
1Mx16 BANK 3
Row Pre Decoder
1Mx16 BANK 2 1Mx16 BANK 1 1Mx16 BANK 0
DQ0
I/O Buffer & Logic Sense AMP & I/O Gate
X-Decoder X-Decoder X-Decoder X-Decoder
CS RAS CAS
Refresh
Memory Cell Array
Column Active
WE U/LDQM
Column Pre Decoder
DQ15
Y-Decoder
Bank Select
Column Add Counter
A0 A1
Address Buffers
Address Register
Burst Counter
A11
BA1 BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.2 / June. 2005
4
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
Rev. 0.2 / June. 2005
5
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD supply relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Rating 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 . 10 Unit
o
C
oC
V V mA W
oC . Sec
DC OPERATING CONDITION (TA= 0 to 70oC)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 Max 3.6 VDDQ+0.3 0.8 Unit V V V Note 1 1, 2 1, 3
-
Note: 1. All voltages are referenced to VSS = 0V 2. VIH (max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL (min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=3.30.3V, VSS=0V)
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
Note 1.
Vtt=1.4V
Symbol VIH / VIL Vtrip tR / tF Voutref CL
Value 2.4 / 0.4 1.4 1 1.4 30
Unit V V ns V pF
Note
1
Vtt=1.4V
RT=500
RT=50
Output
Output
30pF
Z0 = 50
30pF
DC Output Load Circuit
AC Output Load Circuit
Rev. 0.2 / June. 2005
6
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=3.3V)
Parameter CLK Input capacitance A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM DQ0 ~ DQ15 Pin Symbol CI1 CI2 CI/O Min 2.0 2.0 3.0 Max 4.0 4.0 5.5 Unit pF pF pF
Data input / output capacitance
DC CHARACTERRISTICS I (TA= 0 to 70oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6
Symbol ILI ILO VOH VOL
Min -1 -1 2.4 -
Max 1 1 0.4
Unit uA uA V V
Note 1 2
IOH = -2mA IOL = +2mA
Rev. 0.2 / June. 2005
7
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter Symbol Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRC tRC(min), All banks active
Normal
Speed 5 6 7 H 100 2 2 P
Unit Note
Operating Current
IDD1
120 110
mA mA mA
1
Precharge Standby Current IDD2P in Power Down Mode IDD2PS
Precharge Standby Current in Non Power Down Mode
IDD2N
18 mA 18 3 3
IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS
mA
Active Standby Current in Non Power Down Mode
IDD3N
40 mA 35 120 110 210 195 1 400 100 180 mA mA mA 3 uA 1 2
IDD3NS Burst Mode Operating CurIDD4 rent Auto Refresh Current Self Refresh Current IDD5 IDD6
CKE 0.2V
Low power
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY5V66EF6(P) Series : Normal Power / HY5V66ELF6(P) Series : Low Power
Rev. 0.2 / June. 2005
8
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter CAS Latency=3 CAS Latency=2 Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH 5 6 7 H P Unit Note
Min Max Min Max Min Max Min Max Min Max 5.0 1000 10 2.0 2.0 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 4.5 6.0 4.5 6.0 10 2.5 2.5 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 5.5 6.0 5.5 6.0 6.0 1000 10 3.0 3.0 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.5 6.0 5.5 6.0 7.0 1000 10 3.0 3.0 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.5 6.0 6.0 6.0 7.5 1000 10 3.0 3.0 2.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 5.5 6.0 6.0 6.0 10 1000
System Clock Cycle Time
ns ns ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1
Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency=3 CAS Latency=2
Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time
CLK to Data Output in Low-Z tOLZ Time CLK to Data Output in High-Z Time CAS Latency=3 CAS Latency=2 tOHZ3 tOHZ2
Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
Rev. 0.2 / June. 2005
9
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter RAS Cycle Time RAS Cycle Time Operation Auto Refresh Symbol tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 5 6 7 H P Unit Note ns ns ns ns ns ns CLK CLK CLK
Min Max Min Max Min Max Min Max Min Max 55 55 15 60 60 18 42 18 20 1 0 2 100K 63 63 20 42 20 20 1 0 2 100K tDPL + tRP 64 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 63 63 20 42 20 20 1 0 2 120 K 70 70 20 50 20 20 1 0 2 120 K -
RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CAS Latency=3 CAS Latency=2
38.7 100K 15 20 1 0 2 -
CLK CLK CLK CLK CLK CLK CLK ms 1
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note :
1. A new command can be given tRRC after self refresh exit.
Rev. 0.2 / June. 2005
10
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit CKEn-1 H H H H CKEn X X X X CS L H L L L RAS L X H L H CAS L X H H L WE L X H H H DQM X X X X CA RA L H L H H L X X X A9 ball High (Other balls OP code) MRS
Mode
ADDR
A10/AP OP code X
BA
Note
V V
H
X
L
H
L
L
X
CA
V X V
H H H H H H L
X X
L L
L H X
H H
L L
X X V
X
H X L H
L L L H L H L H L H L
L L L X H X H X H X V X
L L L X H X H X H X V
H L H X H X H X H X V
X X X X
X
Entry Precharge power down Exit
H
L
X X X
L
H
Clock Suspend
Entry Exit
H L
L H
X X
X
Rev. 0.2 / June. 2005
11
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
PACKAGE INFORMATION 60 Ball FBGA 10.1mm x 6.4mm
10.10 +/-0.10 0.500 0.10
Unit [mm]
1.1MAX
9.10 REF
0.65 Typ.
6.40 0.10
Bottom View
1.80 0.10
3.90 RFF 1.30 Typ.
0.450 +/- 0.05
0.65 Typ. 0.280 0.05
Rev. 0.2 / June. 2005
12

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